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1. general description the pcf8593 is a cmos 1 clock and calendar circuit, optimized for low power consumption. addresses and data are transfer red serially via the two-line bidirectional i 2 c-bus. the built-in word address register is incremented automatically after each written or read data byte. th e built-in 32.768 khz oscillator circui t and the first 8 bytes of the ram are used for the clock, calendar, and counter functions. the next 8 bytes can be programmed as alarm registers or used as free ram space. 2. features and benefits ? i 2 c-bus interface operating supply voltage: 2.5 v to 6.0 v ? clock operating supply voltage 1.0 v to 6.0 v at 0 cto+70 c ? 8 bytes scratchpad ram (when alarm not used) ? data retention voltage: 1.0 v to 6.0 v ? external reset input resets i 2 c interface only ? operating current (at f scl = 0 hz, 32 khz time base, v dd = 2.0 v): typical 1 a ? clock function with four year calendar ? universal timer with alarm and overflow indication ? 24 hour or 12 hour format ? 32.768 khz or 50 hz time base ? serial input and output bus (i 2 c-bus) ? automatic word address incrementing ? programmable alarm, timer, and interrupt function ? space-saving so8 package available ? slave addresses: a3h for reading, a2h for writing 3. ordering information pcf8593 low power clock and calendar rev. 04 ? 6 october 2010 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 14 . table 1. ordering information type number package name description version pcf8593p dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 PCF8593T so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 2 of 35 nxp semiconductors pcf8593 low power clock and calendar 4. marking 5. block diagram table 2. marking codes type number marking code pcf8593p pcf8593p PCF8593T 8583t fig 1. block diagram of pcf8593 013aaa37 9 pcf8593 osci osco int scl sda oscillator reset i 2 c-bus interface divider control logic address register 00h 01h 02h 03h 04h 05h 06h 07h 0fh control/status hundredth second seconds minutes hours year/date weekdays/months timer alarm or ram reset v ss v dd 08h to alarm control
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 3 of 35 nxp semiconductors pcf8593 low power clock and calendar 6. pinning information 6.1 pinning 6.2 pin description top view. for mechanical details, see figure 24 . fig 2. pin configuration for dip8 (pcf8593p) top view. for mechanical details, see figure 25 . fig 3. pin configuration for so8 (PCF8593T) pcf8593p osci v dd osco int reset scl v ss sda 013aaa380 1 2 3 4 6 5 8 7 PCF8593T 013aaa381 1 2 3 4 6 5 8 7 osci osco reset v ss v dd int scl sda table 3. pin description symbol pin type description dip8 (pcf8593p) so8 (PCF8593T) osci 1 1 input oscillator inpu t, 50 hz or event-pulse input osco 2 2 output oscillator output reset 3 3 input reset v ss 4 4 supply ground supply voltage sda 5 5 input/output serial data line scl 6 6 input serial clock line int 7 7 output open-drain interru pt output (active low) v dd 8 8 supply supply voltage
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 4 of 35 nxp semiconductors pcf8593 low power clock and calendar 7. functional description the pcf8593 contains sixteen 8 bit register s with an 8 bit auto-incrementing address register, an on-chip 32.768 khz oscillator circ uit, a frequency divider and a serial two-line bidirectional i 2 c-bus interface. the first 8 registers (memory addresses 00 h to 07h) are designed as addressable 8 bit parallel registers. the first register (memory address 00h) is used as a control and status register. the memory addresses 01h to 07h are used as counters for the clock function. the memory addresses 08h to 0fh may be programmed as alarm registers or used as free ram locations. 7.1 counter function modes when the control and status register is programmed, a 32.768 khz clock mode, a 50 hz clock mode or an event-counter mode can be selected. in the clock modes the hundredths of a seco nd, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a binary coded decimal (bcd) format. the timer register stores up to 99 days. th e event counter mode is used to count pulses applied to the oscillator input (osco left open -circuit). the event counter stores up to 6 digits of data. when one of the counters is read (memory locations 01h to 07h), the contents of all counters are strobed into capture latches at the beginning of a read cycle. therefore, faulty reading of the counter during a carr y condition is prevented. when a counter is written, other counters are not affected. 7.2 alarm function modes by setting the alarm enable bit of the control and status register the alarm control register (address 08h) is activated. by setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a timer alarm may be programmed. in the clock modes, the timer register (address 07h) may be programmed to count hundredths of a second, seconds, minutes, hours, or days. days are counted when an alarm is not programmed. whenever an alarm event occurs the alarm flag of the control an d status register is set. a timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. the open-drain interrupt output is switched on (active low) when the alarm or timer flag is set (enabled). t he flags remain set until direct ly reset by a write operation. when the alarm is disabled (bit 2 of contro l and status register set logic 0) the alarm registers at addresses 08h to 0fh may be used as free ram.
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 5 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.3 control and status register the control and status register is defined as the memory location 00h with free access for reading and writing via the i 2 c-bus. all functions and options are controlled by the contents of the control and status register (see figure 4 ). fig 4. control and status register timer flag: alarm flag: alarm enable bit: mask flag: function mode: 00 01 10 11 hold last count flag: logic 0: logic 1: stop counting flag: logic 0: logic 1: 76543210 msb lsb 013aaa382 memory location 00h alarm disabled: flags toggle alarm control register to disabled (memory locations 08h to 0fh are free ram space) logic 1: enable alarm control register (memory location 08h is the alarm control register) logic 0: read locations 05h to 06h unmasked logic 1: read date and month count directly 50 % duty factor seconds flag if alarm enable bit is logic 0 50 % duty factor minutes flag if alarm enable bit is logic 0 logic 0: clock mode 32.768 khz clock mode 50 hz event-counter mode test modes store and hold last count in capture latches count count pulses stop counting, reset divider
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 6 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.4 counter registers the format for 24 hour or 12 hour clock mode s can be selected by setting the most significant bit of the hours counter register. the format of the hours counter is shown in figure 5 . the year and date are stored in memory location 05h (see figure 6 ). the weekdays and months are in memory location 06h (see figure 7 ). when reading these memory locations the year and weekdays are masked out when the mask flag of the control and stat us register is set. this allows the user to read the date and month count directly. fig 5. format of the hours counter fig 6. format of the year and date counter fig 7. format of the weekdays and month counter 76543210 msb lsb 013aaa383 memory location 04h (hours counter) unit place ten's place (0 to 2 binary) am/pm flag: logic 0: am logic 1: pm format: logic 0: 24 hour format, am/pm flag remains unchanged logic 1: 12 h format, am/pm flag will be updated hours in bcd format: 7 65 432 10 msb lsb 013aaa384 unit place ten's place (0 to 3 binary) year (0 to 3 binary, read as logic 0 if the mask flag is set) memory location 05h (year/date) days in bcd format: 76 543 210 msb lsb 013aaa385 memory location 06h (weekdays/months) unit place ten's place weekdays (0 to 6 binary, read as logic 0 if the mask flag is set) months in bcd format:
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 7 of 35 nxp semiconductors pcf8593 low power clock and calendar in the event-counter mode, events are stored in bcd format. d5 is the most significant and d0 the least significant digit. the divider is by-passed. in the different modes the counter registers are programmed and arranged as shown in figure 8 . counter cycles are listed in ta b l e 4 . fig 8. register arrangement control/status hundredth of a second 1/10 s seconds minutes hours year/date weekdays/months timer 10 s 10 min 10 h 10 day 10 month 10 day 1/100 s 1 s 1 min 1 h 1 day 1 month 1 day alarm control hundredth of a second alarm 1/10 s 1/100 s alarm seconds alarm minutes alarm hours alarm month alarm timer alarm date control/status d1 d3 d5 free free free timer t1 alarm control alarm alarm d1 d3 d5 d0 d2 d4 t0 d0 d2 d4 free free free alarm timer 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh clock modes event counter 013aaa386
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 8 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.5 alarm control register when the alarm enable bit of the control and stat us register is set (a ddress 00h, bit 2) the alarm control register (address 08h) is activa ted. all alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see figure 9 ). table 4. cycle length of the time counters, clock modes unit counting cycle carry to next unit contents of month calendar hundredths of a second 00 to 99 99 to 00 - seconds 00 to 59 59 to 00 - minutes 00 to 59 59 to 00 - hours (24) 00 to 23 23 to 00 - hours (12) 12 am - - 01 am to 11 am - - 12 pm - - 01 pm to 11 pm 11 pm to 12 am - date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10, and 12 01 to 30 30 to 01 4, 6, 9, and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2, and 3 months 01 to 12 12 to 01 - year 0 to 3 - - weekdays 0 to 6 6 to 0 - timer 00 to 99 no carry -
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 9 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.6 alarm registers all alarm registers are allocated with a co nstant address offset of 08h to the corresponding counter registers (see figure 8 ). an alarm signal is generated when the contents of the alarm registers match bit-by-bit the contents of the involved counter registers. the year and weekday bits are ignored in a dated alarm. a daily alarm ignores the month and date bits. when a weekday alarm is selected, the contents of the alarm weekday and month register selects the weekdays on which an alarm is activated (see figure 10 ). remark: in the 12 hour mode, bits 6 and 7 of the al arm hours register must be the same as the hours counter. fig 9. alarm control re gisters, clock mode memory location 08h timer function: timer interrupt enable: clock alarm function: timer alarm enable: alarm interrupt enable: 7 654 321 0 msb lsb 013aaa387 000 001 010 011 100 101 110 111 no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel 0 1 timer flag, no interrupt timer flag, interrupt 00 01 10 11 no clock alarm daily alarm weekday alarm dated alarm 0 1 no timer alarm timer alarm (only valid when alarm enable in the control and status register is set) 0 1 alarm flag, no interrupt alarm flag, interrupt
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 10 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.7 timer the timer (location 07h) is enabled by se tting the control and status register to xx0x x1xx. the timer counts up from 0 (or a programmed value) to 99. on overflow, the timer resets to 0. the timer flag (lsb of control and status register) is set on overflow of the timer. this flag must be reset by software. the inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register. additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of the alarm control register). when the value of the timer equals a pre-programmed value in the alarm timer register (location 0fh), the alar m flag is set (bit 1 of the control and status register). the inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register). resolution of the timer is programmed via th e 3 lsbs of the alarm control register (see figure 11 ). fig 10. selection of alarm weekdays 76543210 msb lsb 013aaa375 memory location 0eh (alarm_weekday/month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 11 of 35 nxp semiconductors pcf8593 low power clock and calendar 7.8 event counter mode event counter mode is selected by bits 4 and 5 which are logic 10 in the control and status register. the event counter mode is used to count pulses externally applied to the oscillator input (osco left open-circuit). the event counter stores up to 6 digits of dat a, which are stored as 6 hexadecimal values located in the registers 1h, 2h , and 3h. therefore, up to 1 million events may be recorded. an event counter alarm occurs when the event counter regist ers match the value programmed in the registers 9h, ah, and bh, and the event alarm is enabled (bits 4 and 5 which are logic 01 in the alarm control register). in this event, the alarm flag (bit 1 of the control and status register) is set. the inverted value of this flag ca n be transferred to the interrupt pin (pin 7) by setting the alarm inte rrupt enable in the alarm control register. in (1) if the alarm enable bit of the control and status register is reset (logic 0), a 1 hz signal is observed on the interrupt pi n int . fig 11. alarm and timer interrupt logic diagram int 7 654 321 0 76543210 timer overflow interrupt alarm interrupt timer alarm clock/calendar mux timer control timer alarm overflow alarm control clock alarm counter control mode select oscillator control/status register (1) alarm control register 013aaa377
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 12 of 35 nxp semiconductors pcf8593 low power clock and calendar this mode, the timer (location 07h) incremen ts once for every one, one hundred, ten thousand, or 1 million events, depending on the value prog rammed in bits 0, 1 and 2 of the alarm control register. in all other events, the timer functions are as in the clock mode. 7.9 interrupt control the conditions for activating the output int (active low) are determined by appropriate programming of the alarm control register. these conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. an interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrup t is enabled. in all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. in the clock mode, if the alarm enable is not activated (alarm enable bit of the control and status register is logic 0), the interrupt out put toggles at 1 hz with a 50 % duty cycle (may be used for calibration). the off voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 v. a logic diagram of the interrupt output is shown in figure 11 . 7.10 oscillator and divider a 32.768 khz quartz crystal has to be connected to osci and osco. a trimmer capacitor between osci and v dd is used for tuning the oscillator (see section 11.1 ). a 100 hz clock signal is derived from the quartz oscillator for the clock counters. fig 12. alarm control register, event counter mode memory location 08h reset state: 0000 0000 timer function: clock alarm function: timer alarm enable: alarm interrupt enable: 7 654 321 0 msb lsb 013aaa376 000 001 010 011 100 101 110 111 no timer units 100 10 000 1 000 000 not allowed not allowed test mode, all counters in parallel timer interrupt enable: 0 1 timer flag, no interrupt timer flag, interrupt 00 01 10 11 no event alarm event alarm not allowed not allowed 0 1 no timer alarm timer alarm 0 1 alarm flag, no interrupt alarm flag, interrupt
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 13 of 35 nxp semiconductors pcf8593 low power clock and calendar in the 50 hz clock mode or ev ent-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. this allows the user to feed the 50 hz reference frequency or an external high speed event signal into the input osci. 7.10.1 designing when designing the prin ted-circuit board layout, keep t he oscillator components as close to the ic package as possible, and keep all othe r signal lines as far away as possible. in applications involving tight packing of components, shield ing of the oscillator may be necessary. ac couplin g of extraneous sign als can introduce oscillator inaccuracy. 7.11 initialization note that immediately following power-on, all internal registers are undefined and, following a reset pulse on pin 3, must be defined via software. attention should be paid to the possibility that the device may be initially in event-co unter mode, in which event the oscillator will not operate. over-r ide can be achieved via software. reset is accomplished by applying an external reset pulse (active low) at pin 3. when reset occurs only the i 2 c-bus interface is reset. the control and status register and all clock counters are no t affected by reset . reset must return high during device operation. an rc combination can also be ut ilized to provide a power-on reset signal at pin 3. in this event, the values of the pcf8593 must fulfil the following relationship to guarantee power-on reset (see figure 13 ). reset input must be input must be 0.3v dd when v dd reaches v dd(min) (or higher). it is recommended to set the stop counting fl ag of the control and status register before loading the actual time into the counters . loading of illegal states may lead to a temporary clock malfunction. to avoid overload of the internal diode by falling v dd , an external diode should be added in parallel to r r if c r 0.2 f. note that rc must be evaluated with the actual v dd of the application, as their value will be v dd rise-time dependent. fig 13. pcf8593 reset reset pcf8593 v dd 013aaa38 8 v dd r r reset input c r
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 14 of 35 nxp semiconductors pcf8593 low power clock and calendar 8. characteristics of the i 2 c-bus 8.1 characteristics the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer is initiated only when the bus is not busy. 8.1.1 bit transfer one data bit is transferred during each clock pulse (see figure 14 ). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time are interpreted as a control signal. 8.1.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 15 ). 8.1.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver (see figure 16 ). the device that controls the message is the master; and the devices which are controlled by the master are the slaves. fig 14. bit transfer mbc62 1 data line stable; data valid change of data allowed sda scl fig 15. definition of start and stop conditions mbc62 2 sda scl p stop condition sda scl s start condition
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 15 of 35 nxp semiconductors pcf8593 low power clock and calendar 8.1.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 17 . fig 16. system configuration mba60 5 master transmitter receiver slave receiver slave transmitter receiver master transmitter master transmitter receiver sda scl fig 17. acknowledgement on the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 16 of 35 nxp semiconductors pcf8593 low power clock and calendar 8.2 i 2 c-bus protocol 8.2.1 addressing before any data is transmitted on the i 2 c-bus, the device wh ich must respond is addressed first. the addressing is always ca rried out with the first byte transmitted after the start procedure. the clock and calendar acts as a slave receiver or slave transmitter. the clock signal scl is only an input signal but the data signal sda is a bidirectional line. the clock and calendar slave address is shown in ta b l e 5 . 8.2.2 clock and calendar read or write cycles the i 2 c-bus configuration for the different pcf 8593 read and write cycles is shown in figure 18 , figure 19 and figure 20 . table 5. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 1010001r/w fig 18. master transmits to slave receiver (write mode) s 0a slave address register address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment memory register address 013aaa34 6 n bytes
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 17 of 35 nxp semiconductors pcf8593 low power clock and calendar (1) at this moment master transmitter becomes master re ceiver and pcf8593 slave receiv er becomes slave transmitter. fig 19. master reads after setting word address (write word address; read data) s 0a slave address register address a a r/w a data 013aaa041 p 1 auto increment memory register address last byte r/w s1 n bytes (1) acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave no acknowledgement from master auto increment memory register address slave address data fig 20. master reads slave immediatel y after first byte (read mode) s 1a slave address data a1 data acknowledgement from slave acknowledgement from master no acknowledgement from master r/w auto increment register address 013aaa347 auto increment register address n bytes last byte p
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 18 of 35 nxp semiconductors pcf8593 low power clock and calendar 9. limiting values [1] pass level; human body model (hbm), according to ref. 5 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 6 ? jesd22-a115 ? . [3] pass level; latch-up testing according to ref. 7 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport requirements (see ref. 9 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.8 +0.7 v i dd supply current - 50 ma i ss ground supply current - 50 ma v i input voltage ? 0.8 v dd + 0.8 v i i input current - 10 ma i o output current - 10 ma p tot total power dissipation - 300 mw p o output power - 50 mw v esd electrostatic discharge voltage hbm [1] - 3000 v mm [2] - 300 v i lu latch-up current [3] - 100 ma t stg storage temperature [4] ? 65 +150 c t amb ambient temperature operating device ? 40 +85 c
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 19 of 35 nxp semiconductors pcf8593 low power clock and calendar 10. characteristics 10.1 static characteristics [1] typical values measured at t amb = 25 c. [2] when the device is powered on, v dd must exceed the specified minimum value by 300 mv to guarantee correct start-up of the oscillator. [3] event counter mode: supply current dependant upon input frequency. [4] tested on a sample basis. table 7. static characteristics v dd = 2.5 v to 6.0 v; v ss = 0 v; t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage operating mode i 2 c-bus active 2.5 - 6.0 v i 2 c-bus inactive 1.0 - 6.0 v quartz oscillator t amb = 0 c to +70 c [2] 1.0 - 6.0 v t amb = ? 40 c to +85 c [2] 1.2 - 6.0 v i dd supply current operating mode f scl = 100 khz clock mode [3] - - 200 a clock mode; f scl = 0 hz v dd = 2.0 v - 1.0 8.0 a v dd = 5.0 v - 4 15 a pin sda, scl and int v il low-level input voltage 0 - 0.3v dd v v ih high-level input voltage 0.7v dd -v dd v i ol low-level output current v ol =0.4v 3 - - ma i li input leakage current v i = v dd or v ss ? 1- +1 a c i input capacitance [4] --7pf pins osci and reset i li input leakage current v i = v dd or v ss ? 250 - +250 na pin int i ol low-level output current v ol = 0.4 v 1 - - ma i li input leakage current v i = v dd or v ss ? 1- +1 a pin scl i li input leakage current v i = v dd or v ss ? 1- +1 a c i input capacitance [4] --7pf
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 20 of 35 nxp semiconductors pcf8593 low power clock and calendar f scl = 32 khz; t amb = 25 c fig 21. typical supply current in clock mode as a function of supply voltage 001aam493 v dd (v) 06 4 2 4 2 6 8 l dd ( a) 0
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 21 of 35 nxp semiconductors pcf8593 low power clock and calendar 10.2 dynamic characteristics [1] event counter mode only. [2] all timing values are valid with in the operating supply voltage, ambient temperature range, reference to v il and v ih and with an input voltage swing of v ss to v dd . table 8. dynamic characteristics v dd = 2.5 v to 6.0 v; v ss = 0 v; t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit oscillator c osco capacitance on pin osco 20 25 30 pf f osc /f osc relative oscillator frequency variation for v dd = 100 mv; t amb =25 c; v dd = 1.5 v -0.2-ppm f clk(ext) external clock frequency [1] --1mhz quartz crystal parameters (f = 32.768 khz) r s series resistance - - 40 k c l parallel load capacitance - 10 - pf c trim trimmer capacitance 5 - 25 pf i 2 c-bus timing (see figure 21 ) [2] f scl scl clock frequency - - 100 khz t sp pulse width of spikes that must be suppressed by the input filter --100ns t buf bus free time between a stop and start condition 4.7 - - s t su;sta set-up time for a repeated start condition 4.7 - - s t hd;sta hold time (repeated) start condition 4.0 - - s t low low period of the scl clock 4.7 - - s t high high period of the scl clock 4.0 - - s t r rise time of both sda and scl signals --1.0 s t f fall time of both sda and scl signals --0.3 s t su;dat data set-up time 250 - - ns t hd;dat data hold time 0 - - ns t vd;dat data valid time - - 3.4 s t su;sto set-up time for stop condition 4.0 - - s
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 22 of 35 nxp semiconductors pcf8593 low power clock and calendar fig 22. i 2 c-bus timing diagram; rise and fall times refer to v il and v ih protocol scl sda mbd82 0 bit 0 lsb (r/w) start condition (s) bit 7 msb (a7) bit 6 (a6) acknowledge (a) stop condition (p) t su;sta t hd;sta t su;dat t hd;dat t vd;dat t su;sto t low t high 1 / f scl t buf t r t f
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 23 of 35 nxp semiconductors pcf8593 low power clock and calendar 11. application information 11.1 oscillator frequency adjustment 11.1.1 method 1: fixed osci capacitor by evaluating the average capacitance nece ssary for the application layout a fixed capacitor can be used. the frequency is best measured via the 1 hz signal which can be programmed to occur at the interrupt output (pin 7). the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 10 ? 6). average deviations of 5 minutes per year can be achieved. 11.1.2 method 2: osci trimmer using the alarm function (via the i 2 c-bus) a signal faster than the 1 hz is generated at the interrupt output for fast setting of a trimmer. procedure: ? power the device on ? apply reset . routine: ? set clock to time t and set alarm to time t + t ? at time t + t (interrupt) repeat routine. 11.1.3 method 3: direct measurement direct measurement of oscillator output (allowing for test pr obe capacitance).
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 24 of 35 nxp semiconductors pcf8593 low power clock and calendar fig 23. application example 013aaa38 9 scl sda v ss osci osco clock/calendar pcf8593 sda scl master transmitter/ receiver v dd sda scl rr r: pull-up resistor r = t r c b v dd v ss reset v dd (i 2 c-bus) 1 f reset v dd reset
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 25 of 35 nxp semiconductors pcf8593 low power clock and calendar 12. package outline fig 24. package outline sot97-1 (dip8) of pcf8593p references outline version european projection issue date iec jedec jeita sot97-1 99-12-27 03-02-13 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.045 0.17 0.02 0.13 b 2 050g01 mo-001 sc-504-8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. pin 1 index d ip8: plastic dual in-line package; 8 leads (300 mil) sot97 -1
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 26 of 35 nxp semiconductors pcf8593 low power clock and calendar fig 25. package outline sot96-1 (so8) of PCF8593T unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale s o8: plastic small outline package; 8 leads; body width 3.9 mm sot96 -1 99-12-27 03-02-18
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 27 of 35 nxp semiconductors pcf8593 low power clock and calendar 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 28 of 35 nxp semiconductors pcf8593 low power clock and calendar 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 26 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 9 and 10 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 26 . table 9. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 10. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 29 of 35 nxp semiconductors pcf8593 low power clock and calendar for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 26. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 30 of 35 nxp semiconductors pcf8593 low power clock and calendar 14. abbreviations table 11. abbreviations acronym description am ante meridiem bcd binary coded decimal cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit lsb least significant bit mm machine model msb most significant bit msl moisture sensitivity level mux multiplexer pcb printed-circuit board pm post meridiem por power-on reset ppm parts per million rf radio frequency ram random access memory scl serial clock line sda serial data line smd surface-mount device
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 31 of 35 nxp semiconductors pcf8593 low power clock and calendar 15. references [1] an10365 ? surface mount reflow soldering description [2] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [3] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [4] ipc/jedec j-std-020 ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [7] jesd78 ? ic latch-up test [8] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [9] nx3-00092 ? nxp store and transport requirements [10] snv-fa-01-02 ? marking formats integrated circuits [11] um10204 ? i 2 c-bus specification and user manual
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 32 of 35 nxp semiconductors pcf8593 low power clock and calendar 16. revision history table 12. revision history document id release date data sheet status change notice supersedes pcf8593 v.4 20101006 product data sheet - pcf8593_3 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. pcf8593_3 19970325 product specification - pcf8593_2 pcf8593_2 19940829 product specification - pcf8593_1 pcf8593_1 19940606 product specification - -
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 33 of 35 nxp semiconductors pcf8593 low power clock and calendar 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pcf8593 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 6 october 2010 34 of 35 nxp semiconductors pcf8593 low power clock and calendar non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcf8593 low power clock and calendar ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 october 2010 document identifier: pcf8593 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 counter function modes . . . . . . . . . . . . . . . . . . 4 7.2 alarm function modes . . . . . . . . . . . . . . . . . . . . 4 7.3 control and status register . . . . . . . . . . . . . . . . 5 7.4 counter registers . . . . . . . . . . . . . . . . . . . . . . . 6 7.5 alarm control register . . . . . . . . . . . . . . . . . . . . 8 7.6 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.7 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.8 event counter mode . . . . . . . . . . . . . . . . . . . . 11 7.9 interrupt control . . . . . . . . . . . . . . . . . . . . . . . 12 7.10 oscillator and divider . . . . . . . . . . . . . . . . . . . 12 7.10.1 designing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.11 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 14 8.1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.2 start and stop conditions . . . . . . . . . . . . . . . . 14 8.1.3 system configuration . . . . . . . . . . . . . . . . . . . 14 8.1.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.2 clock and calendar read or write cycles . 16 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 static characteristics . . . . . . . . . . . . . . . . . . . . 19 10.2 dynamic characteristics . . . . . . . . . . . . . . . . . 21 11 application information. . . . . . . . . . . . . . . . . . 23 11.1 oscillator frequency adjustment . . . . . . . . . . . 23 11.1.1 method 1: fixed osci capacitor. . . . . . . . . . . 23 11.1.2 method 2: osci trimmer. . . . . . . . . . . . . . . . . 23 11.1.3 method 3: direct measurement . . . . . . . . . . . 23 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 13 soldering of smd packages . . . . . . . . . . . . . . 27 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 27 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 27 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30 15 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 32 17 legal information . . . . . . . . . . . . . . . . . . . . . . 33 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 33 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18 contact information . . . . . . . . . . . . . . . . . . . . 34 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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